A conventional logic circuit employing bipolar transistors is shown in FIG. 1. In FIG. 1, an input signal which changes between two logic states, i.e., the high level state (referred as H level hereafter) and the low level state (referred as L level hereafter) is applied to an input terminal 10. This input signal is applied to the base of a transistor 12 of a first differential amplifier circuit 14 through a capacitor 16. A resistor 18 is connected between the base of the transistor 12 an a power supply terminal 20 with a source voltage Vcc. The first differential amplifier circuit 14 comprises the transistor 12 and a transistor 22, whose emitters are connected with each other.
Load resistors 24 and 26 are connected between the collectors of the transistors 12 and 22 and the power supply terminal 20, respectively. The connection node between the emitters of the transistors 12 and 22 is connected to a reference potential supply terminal 28 via a current source 30. Two transistors 32 and 34 are coupled in parallel between the power supply terminal 20 and the reference potential supply terminal 28 through current sources 36 and 38, respectively. The bases of the transistors 32 and 34 are connected to the collectors of the transistors 12 and 22. Thus, potentials on the collectors of the transistors 12 and 22 are led to the bases of transistors 32 and 34. Thus, currents supplied from current sources 36 and 38 to the transistors 32 and 34 are differentially controlled by the transistors 12 and 22, respectively.
Transistors 40, 42, 44, 46, 48, 50, 52, 54, 46, 58, 60 and 62 constitute a master-slave flip-flop 64 in a type of a double-balance type differential circuit. The transistors 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60 and 62 constitute six differential circuits 66, 68, 70, 72, 74 and 76. The transistors 40 and 42 constitute a second differential circuit 66. The transistors 44 and 46 constitute a third differential circuit 68. The transistors 48 and 50 constitute a fourth differential circuit 70. The transistors 52 and 54 constitute a fifth differential circuit 72. The transistors 56 and 58 constitute a sixth differential circuit 74. The transistors 60 and 62 constitute a seventh differential circuit 76. That is, the emitters of the transistors 40 and 42 are connected in common and then the common emitter connection node thereof is coupled to the collector of the transistor 56. The emitters of the transistors 44 and 46 are connected in common and then the common emitter connection node thereof is coupled to the collector of the transistor 58. The emitters of the transistors 48 and 50 are connected in common and then the common emitter connection node thereof is coupled to the collector of the transistor 60. The emitters of the transistors 52 and 54 are connected in common and then the common emitter connection node thereof is coupled to the collector of the transistor 62. The emitters of the transistors 56 and 58 are connected in common and then the common emitter connection node thereof is coupled to the reference potential supply terminal 28 through a current source 78. The emitters of the transistors 60 and 62 are connected in common and then the common emitter connection node thereof is coupled to the reference potential supply terminal 28 through a current source 80.
The transistors 56 and 58 in the sixth differential circuit 74 differentially drive the transistors 40, 42, 44 and 46. The transistors 60 and 62 in the seventh differential circuit 76 differentially drive transistors 48, 50, 52 and 54.
The bases of the transistors 56 and 62 are connected to each other. Similarly, the bases of the transistors 58 and 60 are connected to each other. Thus, the current source 78 supplies a current controlled by the input signal to the input terminal 10. The current source 80 supplies a current controlled by the same input signal.
The collectors of the transistors 40 and 44 are commonly connected to the power supply terminal 20 through a load resistor 82. The collectors of the transistors 42 and 46 are commonly connected to the power supply terminal 20 through a load resistor 84. The collectors of the transistors 48 and 52 are commonly connected to the power supply terminal 20 through a load resistor 86. The collectors of the transistors 50 and 54 are commonly connected to the power supply terminal 20 through a load resistor 88.
The common collector connector node 90 of the transistor 40 and 44 is connected to the bases of the transistors 42 and 52. The common collector connection node 92 of the transistors 42 and 46 is connected to the bases of the transistors 40 and 54. The common collector connection node 94 of the transistors 48 and 52 is connected to the bases of the transistors 46 and 50. The common collector connection node 96 of the transistors 50 and 54 is connected to the bases of the transistors 44 and 48. The common collector connection node 92 of the transistors 42 and 46 is connected to an output terminal 98.
An operation of the conventional logic circuit, as shown in FIG. 1, will be explained in the following table.
TABLE 1 ______________________________________ I II III IV ______________________________________ Potential P10 on L -&gt; H -&gt; L -&gt; L Input terminal 10 Collector Potential P22 L H L H of Transistor 22 Collector potential P12 H L H L of Transistor 12 Potential P90 on L L H H Connection Node 90 Potential P92 on H H L L Connection Node 92 Potential P94 on L H H L Connection Node 94 Potential P96 on H L L H Connection Node 96 ______________________________________
As shown in Table 1, P10 indicates a potential on the input terminal 10 according to the input signal. P12 and P22 indicate potentials on the collectors of the transistors 12 and 22, respectively. P90, P92, P94 and P96 indicate potentials appearing on the common collector connection nodes 90, 92, 94 and 96 in the master-slave flip-flop 64 comprised of the transistors 42, 44, 46, 46, 50, 52, 54, 56, 58, 60 and 62. Further, symbols H and L in Table 1 denote high level and low level, respectively. For example, the potential P10 is the H level when a current does not flow through the resistor 18. While, the potential P10 is the L level when a current flows through the resistor 18.
Now it is assumed that the input signal applied to the input terminal 10 is initially the L level. Then, the level of the input signal alternately changes between the L level and the H level. Thus, the potential P10 on the base of the transistor 12 changes, as like L.fwdarw.H.fwdarw.L.fwdarw.H . . . . It is also assumed that initially the transistor 48 is turned ON while the transistor 50 is turned OFF. Thus, the potential P94 is the L level while the potential P82 is the H level. It follows that the potential P90 is put to the L level and the potential P92 is put to the H level, according to the nature of the second differential circuit 68. At this time, the transistor 12 is turned OFF while the transistor 22 is turned ON. The potential P12 becomes the H level and this H level potential appears directly at the emitter of the transistor 32. As a result, the transistors 58 and 60 are turned ON, and the transistors 56 and 62 are turned OFF. Accordingly, the current flow routes in the state I will be the route of the load resistor 82.fwdarw.the transistor 44.fwdarw.the transistor 58.fwdarw.the current source 78 and the route of the load resistor 86.fwdarw.the transistor 58.fwdarw.the transistor 60.fwdarw.the current source 80.
Then, when the signal P10 is changed to the H level (operation state II), the conduction states of the transistors 12 and 22 are reversed. Thus, the potential P12 is changed to the L level and the potential P22 is changed to the H level. Due to the changes of the potentials P12 and P22, the conduction states of the transistors 56, 58, 60 and 62 are also reversed. Then, the conduction states of the transistors 44 and 46 at the operation state I are latched by the transistors 40 and 42 of the second differential circuit 66. On the other hand, the transistors 48 and 50 are both turned OFF in the operation state II. The transistor 54 of the fifth differential circuit 72 is turned ON in response to the reverse operation of the seventh differential circuit 76. In this operation state II, currents flow through the route of the load resistor 82.fwdarw. the transistors 40.fwdarw.the transistor 56.fwdarw.the current source 78 and the route of the load resistor 88.fwdarw.the transistor 54.fwdarw.the transistor 62.fwdarw.the current source 80. As a result, the potentials P94 and P96 are reversed but the potentials P90 and P92 are not reversed at the change between the operation states I and II.
When the potential P10 again becomes the L level (operation state III), the transistors 32 is turned OFF and the transistor 12 is turned ON. As a result, the potential P22 is the L level and the potential P12 is the H level. The states of the sixth and seventh differential circuits 74 and 76 are reversed from the operation state II. As a result, the transistors 48 and 50 latch the states of the transistors 52 and 54. Thus, the transistor 50 is turned ON but the transistor 48 is turned OFF. The transistors 44 and 46 also latch the states of the transistors 40 and 42. Thus, the transistor 46 is turned ON but the transistor 44 is turned OFF. In this operation state III, currents flow through the route of the load resistor 84.fwdarw.the transistor 46.fwdarw.the transistor 58.fwdarw.the current source 78 and the route of the load resistor 88.fwdarw.the transistor 50.fwdarw.the transistor 60.fwdarw.the current source 80. As a result, the potentials P94 and P96 are not reversed but the potentials P90 and P92 are reversed at the change between the operation states II and III.
In the operation state IV, as the potential P10 changes to the H level again, the potential become the H level and the potential P12 becomes the L level. As a result, the sixth and seventh differential circuit 74 and 76 are reversed from the operation state III. As a result, the transistors 42 and 44 latch the states of the transistors 44 and 46. Thus, the transistor 42 is turned ON but the transistor 40 is turned OFF. The transistors 52 and 54 also latch the states of the transistors 48 and 50. Thus, the transistor 52 is turned ON but the transistor 54 is turned OFF. In this operation state IV, currents flow through the route of the load resistor 84.fwdarw.the transistor 42.fwdarw.the transistor 58.fwdarw.the current source 78 and the route of the load resistor 86.fwdarw.the transistor 52.fwdarw.the transistor 62.fwdarw.the current source 80. As a result, the potentials P94 and P96 are reversed but the potentials P90 and P92 are not reversed at the change between the operation states III and IV.
According to the operations described in the above, the logic circuit shown in FIG. 1 functions as a master-slave flip-flop which divides the frequency of the input signal into a half.
Recently, the logic circuit or the master-slave circuit have been used in many portable electronic equipments such as a remote control hand set, an IC card, etc. The portable equipments have required as battery as simple as possible. Generally, when a battery voltage drops below about 0.9 volts, the master-slave circuit cannot operate well. Therefore, provision of a logic circuit that is capable of performing the master-slave operation accurately at lower voltages is desirable.
The conventional circuit, as shown in FIG. 1, has a relatively long series route or connection in which two or more base-emitter junctions are included between power supply terminals. For example, the base-emitter junctions of the transistors 40 and 56 are connected in series between the power supply terminal 20 and the reference potential supply terminal 28. Each of the base-emitter junctions has a prescribed voltage, i.e., a so-called base-emitter junction voltage Vbe (minimum voltage required for ON/OFF operation of transistors). In silicon transistors, the base-emitter junction voltage Vbe are about 0.8 volts. Thus, logic circuits having such a series connection of the base-emitter junctions does not operate well at a voltage below 1.6 volts.
As described above, the conventional logic circuit has a problem in that the circuit does not operate unless the power source supplies a voltage about two times the base-emitter junction voltage Vbe.